Journal: Journal of Computer Science and Engineering Research (JCSER), Volume:1, Issue:1, Pages: 24-30 Download pdf
Authors: Khairul Shazwan Mamat, Chia Yee Ooi
Date: 9-2024
Abstract: Memory-based Physical Unclonable Functions (PUFs) are normally used for authentication and key generation for hardware security. Various types of memories, such as SRAM, DRAM, and flash, are explored for their effectiveness as PUFs. SRAM (Static Random-Access Memory) has been a prominent choice for PUF applications due to its reliable start-up pattern, which exhibits variability across different chips due to inherent manufacturing differences. DRAM (Dynamic Random-Access Memory) PUF can be based on start-up pattern, DRAM related latency parameters, or DRAM retention. In this paper, we explored both embedded SRAM and SDRAM of an FPGA to be utilized as PUFs. SRAM is, as expected, shown to be effective and reliable as a PUF. Its start-up pattern is well-established for generating unique identifiers. Although SDRAM shows promising randomness, its bit error rate (BER) is high (exceeding 50%), which significantly impacts its reliability as a PUF. A high BER means that the data obtained from the SDRAM can be unreliable, which is critical for PUF applications where consistency is key. Since most of the system has both SRAM and SDRAM, we recommend that SRAM can be utilized continuously for its established reliability as a PUF. Meanwhile, SDRAM with its strong randomness attributes make it a good candidate for a different role, which is a seed for data obfuscation to scramble or obscure data, especially in scenarios where authentication fails, thus enhancing overall security.
Keywords: Authentication; Physical Unclonable Function; Reliability; Robustness; Randomness
References:
[1]P. Ahr, M. Noushinfar, and C. Lipps, ‘RAM-Based PUFs: Comparing Static-and Dynamic Random Access Memory’, in Workshop on Next Generation Networks and Applications, 2021.
[2] W. Wang, A. D. Singh, and U. Guin, “A Systematic Bit Selection Method for Robust SRAM PUFs,” Journal of Electronic Testing, vol. 38, no. 3, pp. 235–246, Jun. 2022, doi: https://doi.org/10.1007/s10836-022-06006-x.
[3] G. Torrens, A. Alheyasat, B. Alorda, and S. A. Bota, “SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram,” Electronics, vol. 11, no. 1, p. 135, Jan. 2022, doi: https://doi.org/10.3390/electronics11010135.
[4] F. Najafi, M. Kaveh, D. Martín, and M. Reza Mosavi, “Deep PUF: A Highly Reliable DRAM PUF-Based Authentication for IoT Networks Using Deep Convolutional Neural Networks,” Sensors, vol. 21, no. 6, p. 2009, Mar. 2021, doi: https://doi.org/10.3390/s21062009.
[5] J. Miskelly and M. O’Neill, “Fast DRAM PUFs on Commodity Devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 11, pp. 3566–3576, Nov. 2020, doi: https://doi.org/10.1109/tcad.2020.3012218.
[6] M.-S. Kim et al., “Error reduction of SRAM-based physically unclonable function for chip authentication,” International Journal of Information Security, vol. 22, no. 5, pp. 1087–1098, Feb. 2023.
[7] Chen, B., et al. A Robust SRAM-PUF Key Generation Scheme Based on Polar Codes. in GLOBECOM 2017 - 2017 IEEE Global Communications Conference. 2017.
[8] S. S. Kudva et al., "16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 302-304.
[9] M. Laban and Milos Drutarovsky, “Improved Efficiency of PUF Response Reconstruction Method,” Apr. 2020.
[10] Neale, A. and M. Sachdev. A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS. in 2015 IEEE Custom Integrated Circuits Conference (CICC). 2015.
[11] M. Gong, H. Zhang, C. Wang, Q. Tong, and Z. Liu, “Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor,” Microelectronics Journal, vol. 103, pp. 104844–104844, Sep. 2020.
[12] Liu, H., et al., Methods for Estimating the Convergence of Inter-Chip Min-Entropy of SRAM PUFs. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018. 65(2): p. 593-605.
[13] A. Ali Pour et al., "Helper Data Masking for Physically Unclonable Function-Based Key Generation Algorithms," in IEEE Access, vol. 10, pp. 40150-40164, 2022.
[14] K. Liu, X. Chen, H. Pu and H. Shinohara, "A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement," in IEEE Journal of Solid-State Circuits, vol. 56, no. 7, pp. 2193-2204, July 2021.
[15] C.-H. Chang, Chao Qun Liu, L. Zhang, and Zhi Hui Kong, “Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions,” Journal of Low Power Electronics and Applications, vol. 6, no. 3, pp. 16–16, Aug. 2016.
[16] Zhang, S., et al. Evaluation and optimization of physical unclonable function (PUF) based on the variability of FinFET SRAM. in 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). 2017.
[17] Narasimham, B., et al. SRAM PUF quality and reliability comparison for 28 nm planar vs. 16 nm FinFET CMOS processes. in 2017 IEEE International Reliability Physics Symposium (IRPS). 2017.
[18] Liao, Z. and Y. Guan. The Cell Dependency Analysis on Learning SRAM Power-Up States. in 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). 2018.
[19] Liao, Z., et al. The impact of discharge inversion affects learning SRAM power-up statistics. in 2017 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). 2017.
[20] Z. Liao and Y. Guan, ‘Rudba: Reusable user-device biometric authentication scheme for multi-service systems’, in 2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2021, pp. 214–225.
[21] J. Lee, D.-W. Jee, and D. Jeon, ‘Power-up control techniques for reliable SRAM PUF’, IEICE Electron. Express, vol. 16, p. 20190296, 2019.
[22] Pyi Phyo Aung, Nordinah Ismail, Chia Yee Ooi, Koichiro Mashiko, Hau Sim Choo, and Takanori Matsuzaki, “Data Remanence Based Approach towards Stable Key Generation from Physically Unclonable Function Response of Embedded SRAMs using Binary Search”, J. Adv. Res. Appl. Sci. Eng. Tech., vol. 35, no. 2, pp. 114–131, Dec. 2023.
[23] A. Santana-Andreo, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, and F. V. Fernandez, “Reliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of aging,” AEU - International Journal of Electronics and Communications, vol. 176, pp. 155147–155147, Mar. 2024.
[24] A. Kumar, None Manoj Sindhwani, and S. Sachdeva, “An Innovative Architecture of DRAM PUF,” Journal of Integrated Circuits and Systems, vol. 18, no. 2, pp. 1–9, Sep. 2023, doi: https://doi.org/10.29292/jics.v18i2.675.
[25] Y. Zheng, Z. Huang, L. Li, C. Xie, Q. Wang, and Z. Wu, “Implementation and Analysis of Hybrid DRAM PUFs on FPGA,” Oct. 2021, doi: https://doi.org/10.1109/nana53684.2021.00074.